A processor generally can perform either a read operation or a write operation but not both upon a memory array, such as a random access memory (RAM) array, during a single clock cycle. This type of memory is sometimes referred to as single-port memory to contrast it with dual-port memory, which is a type of memory that accommodates a processor performing both a read operation and a write operation during a single clock cycle. As a dual-port memory cell occupies a greater amount of space on an integrated circuit chip than a cell of the aforementioned (single-port) type of memory, a hybrid type of memory that is sometimes referred to as pseudo-dual-port (PDP) memory was developed that can accommodate both a read operation and a write operation during a single clock cycle while occupying less chip area than an equivalent amount of true dual-port memory. A characteristic of PDP memory is that a read operation always immediately precedes a write operation by one half clock cycle.
As illustrated in FIG. 1, a conventional PDP memory system 10 includes, in addition to a memory array 12 and control logic 14, a write address register 16, a read address register 18, and an address multiplexer (MUX) 20. The presence of an address MUX that selects or multiplexes both a read address and a write address in association with a single clock cycle is a characteristic of PDP memory.
Timing and control logic 14 generates a delayed clock signal or address clock (“ADDR_CLK”) from the master clock signal (“CLOCK”) as well as signals that directly control memory array 12, such as signals along the lines of those commonly referred to in memory systems as write enable and read enable and other control signals. As illustrated in FIG. 2, the write address that is input to PDP memory system 10 (FIG. 1) is registered into write address register 16 in response to the rising edge of the address clock at time 22. Likewise, the read address that is input to PDP memory system 10 (FIG. 1) is registered into read address register 18 in response to the rising edge 22 of the address clock. The write and read addresses that are registered or stored in address registers 16 and 18, respectively, are thus presented to the input of address MUX 20 at time 24. Note the delay T1 between the rising edge 22 of the address clock and the registering of the read and write addresses at time 24. This delay T1 is inherent in the operation of each of write and read address registers 16 and 18.
Timing and control logic 14 also generates a MUX control signal (“SELR”) that is similar to the master clock and address clock signals. As indicated by the curved arrow 28, the length and duty cycle of the MUX control signal is determined by a timer (not separately shown) in timing and control logic 14. While the MUX control signal remains high, address MUX 20 selects or passes the registered read address through to its output. Note the delay T2 between time 24 and the time 26 at which MUX 20 outputs the read address. This delay T2 is inherent in the operation of MUX 20. For example, a first exemplary read address (“RA_A”) is output by MUX 20 at time 26.
In response to the first exemplary read address, memory array 12 (FIG. 1) reads the memory location represented by RA_A and, at time 30, outputs a first exemplary data value (“READ DATA_A”) that was stored at that memory location. Note the memory access time represented by the interval between time 26 and the time 30. This memory access time is inherent in the operation of memory array 12. Also note the total time, commonly referred as clock-to-Q time (“T_CLK-Q”), between the rising edge 30 of the clock signal and the output data appearing at the data output of memory array 12. The reading of the first exemplary data value represents the completion of the first half of this exemplary read-write cycle. Additional read and write addresses, such as a second exemplary read address “RA_B,” a second exemplary write address “WA_B,” a third exemplary read address “RA_C,” and a third exemplary write address “WA_C,” can be input to PDP memory system 10 and processed in the same manner described herein. However, for brevity, only the read operation associated with the first exemplary read address is described herein.
The second half or “write” half of the exemplary read-write cycle begins at time 32 when the MUX control signal transitions from high to low. While the MUX control signal remains low, address MUX 20 selects or passes the registered write address through to its output. Note the same delay T2 between time 32 and the time 34 at which MUX 20 outputs the write address. For example, a first exemplary write address (“WA_A”) is output by MUX 20 at time 34. In response to the first exemplary write address, memory array 12 writes input data (not shown) to the memory location represented by WA_A. As noted above, for brevity, and because persons skilled in the art understand the operation of PDP memory system 10, neither this write operation nor subsequent read or write operations are described in further detail herein.
It would be desirable to increase the speed at which memory operations can be performed in a PDP memory system.